Silicon dioxide has been used as a gate oxide material in integrated circuits for decades. As integrated circuits have decreased in size, the thickness of the silicon dioxide gate dielectric has steadily decreased to increase the gate capacitance and thereby drive current, raising device performance. However, as the gate dielectric thickness scales below 2 nm, leakage currents due to tunneling increase drastically and leads to high power consumption and reduced device reliability. In order to allow increased gate capacitance with the associated leakage effects, the silicon dioxide gate dielectric has been replaced with a high-k material.
Processes for depositing spacers around high-k metal gate structures are typically kept at low to moderate temperatures so that diffusion of halo or extension implants or of layers containing oxygen does not affect electrical properties of the high-k gate insulator. Conventionally, plasma enhanced chemical vapor deposition (PECVD) processes are used to deposit spacer layers at low temperatures. However, current PECVD processes result in non-uniform spacer thicknesses across isolated and dense device areas on semiconductor substrates. Non-uniformity of spacer thicknesses leads to different implant profiles resulting in electrical variation.
Accordingly, it is desirable to provide integrated circuits having improved spacers and methods for fabricating integrated circuits having improved spacers. In addition, it is desirable to provide methods for fabricating integrated circuits which form spacers at lower temperatures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.